I applied through university. The process took 3 weeks. I interviewed at Ambarella
Interview
On campus career fair submitted resume, phone interview. Totally technical, questions on clock skew/jitter, string detector, verilog data width and implementing gate with MUX
Interview questions [1]
Question 1
Compare the advantage of shift register and FSM in implementing string detector
I applied through university. The process took 4 weeks. I interviewed at Ambarella (Santa Clara, CA) in Feb 2013
Interview
Submitted resume at the career fair, and then get e-mails to have phone interview. Three rounds of phone interviews.
Interview questions [1]
Question 1
1. Basic circuit design and logic design question
2. Basic verilog question (e.g. verilog module to swap 2 variables, 4-to-1 mux etc.)
3. Write a verilog testbench module which generates 2 output signals:
1) clock - at 1GHZ
2) reset - asserted (1) for first 100 cycles and then deasserted (0)
4. 8 entry FIFO module
5. What are the 2 components of a chip power and how will you reduce each one?