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      ASIC Clocks Engineer Interview

      20 Apr 2021
      Anonymous interview candidate
      San Jose, CA

      Other ASIC Clocks Engineer interview reviews for NVIDIA

      ASIC Clocks Engineer Interview

      15 May 2026
      Anonymous interview candidate
      San Jose, CA
      No offer
      Neutral experience
      No offer
      Positive experience
      Easy interview

      Application

      I applied through an employee referral. I interviewed at NVIDIA (San Jose, CA) in Mar 2021

      Interview

      - First 2 rounds are phone screening, 45 minutes each. - The next round is virtual on-site 6 rounds (mostly 4 technical and 2 behavioral). - Last round will be an HR round.

      Interview questions [1]

      Question 1

      1st round had 5 questions: 1. Some questions on basic digital design like design a NAND/NOR gate using MUX. 2. 1 basic scripting question. 3. Sequence detector FSM question. 4. Fibonacci series..with and without recurring function.
      Answer question
      6
      Average interview

      Application

      I applied online. I interviewed at NVIDIA (San Jose, CA) in Apr 2026

      Interview

      2 phone technical rounds each lasted 1 hour. They asked more about SVA, SV, UVM basics and programming skills. And they was a screening test before these interviews that happended in hacker rank. New grad - ASIC Clocks Design Verification Role.

      Interview questions [1]

      Question 1

      gave a pulse detector circuit and asked to identify cases when circuit breaks?
      Answer question

      ASIC Clocks Engineer Interview

      8 Apr 2024
      Anonymous interview candidate
      Santa Clara, CA
      No offer
      Neutral experience
      Average interview

      Application

      I applied online. The process took 2 days. I interviewed at NVIDIA (Santa Clara, CA) in Feb 2024

      Interview

      This was a new grad position. Two rounds- coding in the language preferred and the next round was technical questions based on Physical Design. Knowledge of Perl was expected. Puzzle based digital design questions were also asked.

      Interview questions [4]

      Question 1

      Design a MUX using only NOT, AND and OR gates
      Answer question

      Question 2

      What is clock domain crossing?
      Answer question

      Question 3

      How do you overcome CDC issues? Detailed questions on each method
      Answer question

      Question 4

      What is grey counter encoding and how is it used to overcome CDC?
      Answer question
      1