# Analog engineer Interview Questions

# 703

Analog Engineer interview questions shared by candidates### How to make sure the 2-stage opamp is stable? How does the compensation work?

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Using Miller compensation. A compensation capacitor across the 2nd stage to create pole splitting. A series resistor to the cap might be needed to solve the rhp zero problem Less

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Using compensation capacitor, which makes the low frequency pole's frequency become lower and high frequency pole's frequency higher, so OPmap is more stable. Less

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Using compensation network including capacitor and resistor and monitoring the phase margin and gain margin as well. Less

### You have to design an LDO with an output voltage of 2V and a supply of 3.6. What is the problem and how do you solve it?

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The question was not about efficiency, since the answer was about voltage rating of devices. It was for experienced designer. Less

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Were this questions for a graduate vacancy? or experienced Analog designer (2-3 years) Less

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From the formulation of the question it was clear that there was a voltage stress on the device, but I needed informations on the technology to answer that (maximum voltage rating, ..). I didn't obtain any detail. I could not think of any solution to the problem (I was assuming CMOS technology), when he told me: you use a DMOS as a pass-device. Well, he did not even say that the technology was BCD.. Less

### Sketch the voltage across a capacitor when charged by a constant current source

3 Answers↳

I answered the question along with the diagram and explained in detail

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v(t)=integral i(t)dt.........so if the current source is constant then the voltage will increase linearly. Less

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It will be zero since current is constant

### Explain why virtual short happen in opamp?

3 Answers↳

in op amp the input resistance is very high due to this very small current (practically zero) flow through the input terminal to op amp so this implies that at both input point which directly entering into the op amp must have same potential. Less

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In an op-amp the voltage gain is very high (ideally 10^5) But the output is limited by the power supply voltage of, maybe 12V . So the differential input can not be more than around 0.12 mV for linear operation. So (v+ - v-) is very small, approximately zero. So v+ and v- may be considered equal for all practical purposes. So thare is a virtual short as both input terminals are at the same potential. 'Virtual' because in reality there is no current flow between the two terminals. Less

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as we know there are two terminals in the op amp .. so the condition of virtual short circuit does not happen everytime .. it's present only when there is negative feedback... not in case of positive feedback ... only condition is negative feedback with AB>>1 . i hope this helps. Less

### Q2: A pnp transistor with its base connected to a voltage source, the V source is connected to a +10V source. The emitter of the transistor is connected to a resistance, and then to the same +10V source. The collector side is connected to a capacitor, which is not charged at t=0-. Given the graph of Vsource = 10 V stepping up at t = 0 to further, draw the graph of Vout. Vout is between the point of collector and capacitor.

3 Answers↳

I just made it back from Lutron's HQ and I was asked for the same question. My first approach will be identifying a PNP BJT, and elaborating all 4 BJT operating regions. Before t = 0, since q = 0, by using Q = CV, we can tell that the voltage across the capacitor is 0. Hence, Vo = -10V before t = 0. Recall the capacitor's current equation: I = C*(dv/dt), we can solve for the slope of changing voltage -> dv/dt = I/C. Here, I is simply the BJT's collector current, which can be found by looking at the BJT's emitter current. Given that the (beta) parameter is infinite, we see the base current to be 0. Now, at this point, we need to look for I_E. Since the R is given to be 9.3k, and VEE = 10V, it is natural to assume V_EB = 0.7V, and thus the voltage across R = 9.3V. Therefore, I_E = 9.3/9300 = 1mA. Voila, we now values for all currents: I_E = I_C = 1mA, and I_B = 0A. Plug the I_C value into the equation: I_C/C = dv/dt (C = 1uF). We know that the slope of the voltage change is 1000V/second, or 1 Volt per millisecond. Now, we know the capacitor voltage raises at 1V/ms from -10V, but we also need to know where is the upper limit. Looking back to the BJT basics about operating regions and BJT's 2-diode model, it is not hard to identify that this PNP BJT must operate in "Saturation" region (NOT IN "ACTIVE" REGION!). The boundary of that region is V_BC <= 0.7V (I hope everybody is able to solve for this). Hence, 0.7V will be the upper limit for capacitor voltage. At this point, you will have a flat line at Vo = -10V before t = 0. and raises at 1V/ms for 10.7ms and hit Vo = 0.7V. From t = 10.7ms and on, the Vo stays at 0.7V. Less

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ANS: Vout should be constantly -10V until t=0, and will hit V=0 V linearly from V=-10 V after t=0. Less

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Hi, Can you explain why it linearly increases? Are you assuming that Collector is tied to -10V? The pnp transistor is completely cutoff for the given biasing. The only way the capacitor is going to charge is through leakage currents. It is very slow and takes a lot of time. Please advise me if my analysis is correct. Less

### Solve the gain of a non-inverting op amp. Suppose the input to the op amp was a 2.5 VAC source with a 2.5 V DC offset. Alter the op amp so there is no offset on the output voltage.

2 Answers↳

Turn the op amp into a differential amplifier (put a 2.5 VDC source on the inverting input to subtract the offset off before amplifying). Less

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There's quite an extended back and forth in actual interviews for questions like this, so nothing quite like real practice. The Prepfully National Instruments Analog Hardware Engineer experts have actually worked in this role, so they're able to do an honest-to-God accurate mock, which really puts you through the paces. prepfully.com/practice-interviews Less

### Experience using LABVIEW

2 Answers↳

Through questions like this, interviewers are mostly trying to test your skillset (and its relevance to the role) as robustly as possible, so be prepared for multiple offshoots and followups. It could be a useful exercise to do mocks with friends or colleagues in National Instruments to get a real sense of what the interview is actually like. Alternatively Prepfully has a ton of National Instruments Analog Hardware Engineer experts who provide mock interviews for a pretty reasonable amount. prepfully.com/practice-interviews Less

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Worked on prjct and used LABVIEW.

### why is matching required?

2 Answers↳

Maximum power transfer.

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Matching in MOSFET transistor inverters is necessary because the electrons that move in the NMOS transistor move at a faster rate than the holes that move in the PMOS transistor. This means when a signal is received, the NMOS will react before the PMOS. To equalize this, they transistors must be matched (by adjusting their widths) so that their transition times are the same. Less