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Asic design engineer Interview Questions

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using a simple logic gate, convert a SET type flop to a RESET type flop

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add inverter to D input as well as Q output of the flop

At the input of D give S_bar*D signal. Where S is the set signal.

Qnew = Qorig * Set_Bar

Tell me about yourself and work experience? Explain ASIC flow? What is Scan chain insertion? USe? What is scan chain reordering? Why macros are placed preferably at boundary and not at centre? What all physical only cells you cam across ? Explain? Checks before placement? How do you fix timing at Place? Difference between CCD and CTS? What is HFNS? Why it is not done at syn? Aim of CTS? What happens in route? What are NDR ? Explain side flows? Types of placement blockages? What is derate? what is LVS? what is FEV? Kind of buffers used for CTS? How do you select them?

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Asked to design a FSM

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Mainly focused on Low power as I said I am interested in low power. Asked about timing analysis STA setup hold and synthesis. Some basic rtl design with verilog vhdl.Basic CMOS modeling NAND gate and NOR gate. IN HR round as i was fail in one of the subject was asking about that subject but as i performed well they consider that.

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DESIGN A VERILOG MODULE HAVING INPUT FROM 1 TO 100 IN RANDOM ORDER. AFTER RECEIVING 99 NUMBER GIVE 100TH NUMBER AS OUTPUT

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Fifo depth calculation 80/10 and 8/10.

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Psychological and Analytic questions would take a conscious presence of mind to go through, The question includes technical knowledge with twists

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