# 124

Asic Verification Engineer interview questions shared by candidates

## Top Interview Questions

Sort: Relevance|Popular|Date
ASIC Verification Engineer was asked...9 September 2010

### You have 2 pieces of rope, each of which burns from one end to the other in 30 minutes (no matter which end is lit). If different pieces touch, the flame will transfer from one to the other. You cannot assume any rope properties that were not stated. Given only 1 match, can you time 45 minutes?

Make a T. Simple

Take one rope (Rope A), place it down as a circle. Light match and start burning rope A at the tips that are touching. When the rope completely burns out, 15 minutes will have passed (since both ends are burning and being consumed at once). Hold the second rope (Rope B) straight and place one end so that it will immediately catch fire when the two burning points from (Rope A) finally touch and are just about to burn out. Thus 15 minutes on Rope A + 30 minutes on Rope B gives you 45 mins. Less

** You cannot assume any rope properties that were not stated Burn like this *-------- ===&gt; After 30mins, Rope A finished burning, and both ends of Rope B start burning Less

### (Unexpected) What the types of caches?

two types: fully associative cache and N-way associative cache

1. Fully Associative. 2. Direct Mapped. 3. Set Associative

L1, L2 and L3 caches

### how do you build a mux out of xor gates?

Oh that is so not true.......!

http://digitalelectronics.blogspot.co.il/2005/11/mux-out-of-xor.html

The answer is you can NOT derive the equation of XOR and MUX by yourself, you will see Less

### Write the base-11 representation of the decimal number 175.

14A

using base-divsion

Its 14A

Hi, Can you explain what was question about " arbiter design" and "transistor level design of registers". Thanks a lot for your help. Less

Hi I just want to ask if you were an undergraduate or graduate (Masters) student when taking the interview? Less

general not very hard, as this is a new graduate position

### FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.

The interviewer to be clueless about HDL...

I was taken aback by the statement, especially since I am an FPGA designer that uses both Verilog and System Verilog at my current job. To respond to the statement, I simply assured the interviewer that I was more than capable of using both HDL languages at a near-expert level as demonstrated by my background. Less

### What are the five stages of a classic RISC pipeline?

Fetch, Decode, Execute, Memory Access, Writeback

Instruction Fetch; Instruction Decode; Memory Access; Execute; Write back

### There are two large arrays filled with random 64-bit signed numbers. How do you determine what are the common numbers in the arrays? Give an algorithm that is linear in complexity. You can use unlimited memory.

Hashtable

Since you can use unlimited memory, Get a memory of size 2^64 deep each of 1 bit. 1. Initialize this memory with all zeros - o(1) 2. Take each number in array 1, point this as address to memory, Fill this as 1 - o(n) 3. Take each number in array 2, and go and read the memory using this as address, if it hits a 1, they are common numbers - o(n) Total complexity = o(n) Less