Companies rely on verification engineers to ensure that their products work as intended. Prepare to answer questions that will assess your ability to design and implement product testing methods. Expect the interviewer to evaluate your communication and documentation skills – these are essential when working with product designers.

1,797 Verification Engineer interview questions shared by candidates

Here are three top product verification engineer interview questions and tips on how to answer them:

How to answer: This question gives you the chance to demonstrate that you understand what the role entails, while showcasing your specific skills. A concise answer that clearly illustrates your approach to verification engineering will signify your value to the interviewer and the company.

How to answer: Use this question as an opportunity to demonstrate your communication skills and your ability to work with a team. Make it clear to the interviewer that you value input from the product designers and that you don't hesitate to ask questions when necessary. The interviewer will also assess your analytical skills when you answer this question. Explain your information-gathering process and how you apply that information as concisely as possible.

How to answer: Prepare to demonstrate that you are familiar with a range of verification engineering techniques. Make sure you mention methods specific to the products produced by the company that you are interviewing with.

ASIC Verification Engineer was asked...9 September 2010

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Make a T. Simple

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Take one rope (Rope A), place it down as a circle. Light match and start burning rope A at the tips that are touching. When the rope completely burns out, 15 minutes will have passed (since both ends are burning and being consumed at once). Hold the second rope (Rope B) straight and place one end so that it will immediately catch fire when the two burning points from (Rope A) finally touch and are just about to burn out. Thus 15 minutes on Rope A + 30 minutes on Rope B gives you 45 mins. Less

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** You cannot assume any rope properties that were not stated Burn like this *-------- ===> After 30mins, Rope A finished burning, and both ends of Rope B start burning Less

Verification Engineer was asked...11 October 2016

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Is the histogram processor similar to MIPS or RISC processor, I think histogram is very specific to GPU application? Less

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It need not add up to 1. In system verilog, typical use of dist does not constrain this. It can be 60:60:60 -- which means probability of 1,2, 3 is 1/3rd. Less

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The histogram processor is something custom. It could be correlated to the DLX pipeline because of memory bottlenecks and dependencies. Less

Digital Design/Verification Engineer was asked...16 March 2011

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Without an enable bit on at least one of the mux's the maximum inputs would be 7. Less

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I don't see it being possible with three standard 4-1 muxes... Using 4, this question is straight forward... The two selects of each mux are your 8 inputs... tie out put of each mux to the (11) case input to the mux. Less

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We need 3 4:1 MUX and a And gate. Are we allowed to use 'and' gate?

Senior Hardware Verification Engineer was asked...30 January 2010

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Write the number in binary and count the number of ones in that.If the number os ones is only 1 then it the number is indeed a power of 2 Less

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For an integer n: If n is less than 1, return false. If the bitwise & of n and n-1 is 0, return true. Otherwise, return false. Less

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I think the main idea is to use recursion function, for the integer which is larger than 0, if it is 1 return true, else return function(n-1) Less

Design Verification & Test Engineer was asked...21 September 2010

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Needs two weighing at most: 1. Put {1, 2, 3} on LHS and {4, 5, 6} on RHS. 2. If LHS and RHS are equal 7 is the lighter one. else discard heavier of previously weighed group. Now we have a group 3 stones left. Lets call them A, B, C. 3. Put A on LHS and B on RHS. 4. If LHS and RHS are equal C is the lighter one. else lighter or LHS or RHS is the lighter one. Voila! Less

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Two tries. 1st try: 3 : 3, 7th is fake if equal; otherwise, 2nd try: 1:1 picked from the light triple in 1st try. the lighter one is fake if any, the third one fake otherwise. Less

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Trail 1: At random weigh two stones vs. two stones (3 sitting on the side) A: Of the 4 on the scales if one side weighs more then the other then weigh one on each side (since one of them must be heavier) B. If the 2 vs 2 are equal then at random weigh 2 (one on each side) of the three left on the side. If they are the same then the 3rd one that never got weighed is the heaviest. Simple case of process of elimination by grouping (Divide and Test) Less

Verification Engineer was asked...11 July 2011

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No, you need to also check for the second_smallest as well. For instance your code does not work for the sequence of "10,20,15". Less

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You can do it in O(n); for(i=0 ; isecond_small) continue; else { if(a[i]>small) second_small = a[i]; else { second_small = small; small = a[i]; } } } } Less

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Quick select

Verification Engineer was asked...28 February 2012

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Will verify all cases for 3 bit- 2^3*2^3 Whereas will only overify corner cases for 64 bit adder Less

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by writing coverage, adder 3-bit we have to check the upper case and lower case ,and same 64 bit also we have to check the lower case as well as upper case and then cross 3 bit and 64 bit. Less

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full scan and partial scan

Verification Engineer was asked...9 April 2014

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All UVM phases are bottom-up except the build phase which is top down (because the parent components have to be constructed already when the child components are built). Less

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Neither bottom up nor top down The run phase tasks of all UVM components run in parallel Less

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None

Senior Verification Engineer was asked...21 June 2018

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Answer 32 Best case write = 160 data in 160 cycles Worst case read = ( 160 * 8/10) = 128 data in 160 cycles Depth = 160 - 128 = 32 Less

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In this case : 20 Data + 80 Valid Data + 80 Valid Data + 20 Data For best case , we have 160 Data writes in 160 clock cycles . For worst read case : In 10 clocks 8 data will be read In 160 clocks (8*160)/10 i.e. 128 data reads So depth of fifo = 160 -128 =32 Less

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In this case , we can have several combinations like : 20 Data + 80 Valid Data + 80 Valid Data + 20 Data For best case of write 160 data will be written in 160 cycles . For worst case of read : 8 data will be read in 10 clock cycles And in 160 clock cycle ,it will read (8*160/10) i.e. 128 Fifo depth is 160-128 =32 Less

Senior Hardware Verification Engineer was asked...30 January 2010

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out = (A NAND (B NAND B))

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OUT = (A NAND (B NAND 1)) or out = (A NAND (B NAND B)) like what anonymous said. Less

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out = ((A NAND A) NAND (A NAND A)) NAND (B NAND B)