Senior asic verification engineer Interview Questions


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Senior ASIC Design Verification Engineer was asked...20 June 2014

(Unexpected) What the types of caches?

3 Answers

two types: fully associative cache and N-way associative cache

1. Fully Associative. 2. Direct Mapped. 3. Set Associative

L1, L2 and L3 caches

PLX Technology

What is a parametrized class?

1 Answers

Parameterised classes are same as parameterised modules in verilog. parameters are like constants local to that particular class. Less

SmartSoC Solutions

Related to SV + UVM + Puzzles + Perl and other scripting language


Difference Between Associative array and Dynamic Arrya


Design an arbiter. This was detailed and went on for the whole 45+ mins.

Test and Verification Solutions

Questions asked were based on the profile and the experience


Full adder circuit, FIFO, Capacitance effect, C, Verilog


My previous experience, as well as a few mock examples related to verification and what my process would be

SolarFlare Communications

Using constrained randomization what types of functional coverage would you expect to see on a PCIe bus?


1. Talk about your work experiences and skills? 2. Mention two substantial technical challenges/great achievements and how you resolved them? 3. What is a singleton and how you create it and what are examples in UVM? 4. 10 CPU stages pipeline each of delay 10 ns, how long does it take to run 100 instructions? 5. Write a C code to know if the machine is big endian or little endian? 6. A Test failed and the designer came back and told you to change something to get the test work, you did that and the test case passed! Can you elaborate on this mentioning what the issue was and how to fix it. 8. you have numbers from 1 to 100 put in an array, you put the numbers in the array but the array length was less than 100, so it is missing a number. The array is shuffled and not sorted. Sketch an algorithm to get that number and mention its big O for performance and capacity? 9. You have an unsorted array, you want to find an 3 elements in the array in which their sum is equal to a specific number? 10. Write Verilog code for posedge/negedge detector? 11. Deep SystemVerilog assertions questions 12. Deep UVM questions (monitors with multiple analysis ports connections to scoreboard, how to collect input stimuli from the DUT (via monitor or sequence/sequencer, difference between p_sequencer/m_sequencer, UVM vertical and horizontal reuse, write code for TRANSLATION sequence, How to enable UVM acceleration in Emulation, etc.) 13. Deep SystemVerilog constrained random questions 14. Deep code optimizations, performance, capacity questions 15. Deep Emulation questions 16, Verify an arbiter using assertions 17. Sketch an algorithm to get the greatest K of an unsorted array. What is the BiG-O notation? 18. Write code to rotate a matrix. What is the BiG-O notation? 19. Power and clock optimizations questions. 20. Deep verification questions 21. UVM Register Layer Very deep questions

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