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Verification engineer Interview Questions

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Questions were asked on verilog and system verilog. Some famous puzzles and aptitude questions were asked. In manegerial round my errors of written round were discussed.

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Answer with confidence. Show the attitude of learning new things. Show genuine interest about the role.

Hi, Could you please tell me what was the section-wise break up of the number of questions.

And a few topics covered in analog and digital which you remember

UVM question : Assuming, UVM environment has 3 different agents having scope to their own interfaces. On driving wrong stimuli on agent1, there will be error pin asserted on interface3(monitor of agent2 sees this). soon after error-pin assertion, there should be a read transaction from agent2. How do you make sure your agent2 drives a read transaction on every wrong stimulus from agent1, which was seen on a monitor of agent2 ?

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Wats the difference between latch and flip flop. What is multiplexer? What is Demultiplexer Types of flip flop Solve the boolean function Data types in verilog

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Asked about the AXI protocol and it's verification test plan.

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What do you know about ARINC 429 protocol in terms of railways security. Rolling stock knowledge etc.

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Mostly on Digital systems design, fsm's, timing analysis and computer architecture.

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Describe the uvm environment, deep copy & shalow copy, diff between mailbox & queue etc. Project description.

1 Answer

Factory writing for non QA scenarios

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They started with project related questions.

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Difference between latch and ff, diff b/n system verilog and verilog, difference between blocking and non blocking,

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