verification engineer interview questions shared by candidates
Questions were asked on verilog and system verilog. Some famous puzzles and aptitude questions were asked. In manegerial round my errors of written round were discussed.
Answer with confidence. Show the attitude of learning new things. Show genuine interest about the role.
Hi, Could you please tell me what was the section-wise break up of the number of questions.
And a few topics covered in analog and digital which you remember
UVM question : Assuming, UVM environment has 3 different agents having scope to their own interfaces. On driving wrong stimuli on agent1, there will be error pin asserted on interface3(monitor of agent2 sees this). soon after error-pin assertion, there should be a read transaction from agent2. How do you make sure your agent2 drives a read transaction on every wrong stimulus from agent1, which was seen on a monitor of agent2 ?
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