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Verification Interview Questions


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UVM question : Assuming, UVM environment has 3 different agents having scope to their own interfaces. On driving wrong stimuli on agent1, there will be error pin asserted on interface3(monitor of agent2 sees this). soon after error-pin assertion, there should be a read transaction from agent2. How do you make sure your agent2 drives a read transaction on every wrong stimulus from agent1, which was seen on a monitor of agent2 ?

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may i know what is the answer you have given to this question?

Use a analysis port to transport the error pin data back to sequencer of agent 2. Create a sequence inside the sequencer and start the sequence inside the write method implementation of the analysis imp. Make sure the sequence priority is high as compared to the default sequences run on the Agent 2 sequencer.

the sequencer of agent 2 can use its p_sequencer handle to access the error pin signal in the monitor. based on which the high priority read txn can be sent

Wats the difference between latch and flip flop. What is multiplexer? What is Demultiplexer Types of flip flop Solve the boolean function Data types in verilog

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Asked about the AXI protocol and it's verification test plan.

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What do you know about ARINC 429 protocol in terms of railways security. Rolling stock knowledge etc.

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Mostly on Digital systems design, fsm's, timing analysis and computer architecture.

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Describe the uvm environment, deep copy & shalow copy, diff between mailbox & queue etc. Project description.

1 Answer

How to design 3-bit synchronoud counters?

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Factory writing for non QA scenarios

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They started with project related questions.

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1. Some resistive networks will be given to you and you have to Req. 2. Capacitor charging and discharging profiles. 3. Waveform translation.

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