We seek a skilled and delivery-focused FPGA Engineer to develop RTL code and implement FPGA-based digital designs, working from specification stage through to system integration. Projects will range from mid-scale to multi-million gate designs involving the latest generation of high-speed serial protocols, DSP pipelines, and control logic — delivered on time and to production quality standards.

Job Position : FPGA RTL Engineer (FPGA Design, Verification & High-Speed Interface Development)

Experience : 2 – 15+ Years

Location : Gurugram/Bengaluru

Key Responsibilities

1. Requirements Understanding & Architecture Definition

Customer Requirements & Product Definition

Engage with product and systems teams to thoroughly understand design intent before committing to implementation:

• Study and interpret customer requirements and product definition documents; raise clarifications and track requirement changes
• Translate system-level requirements into block-level technical constraints: gate count budget, clock frequencies, interface bandwidths, and latency targets
• Participate in customer-facing or internal technical reviews to align on scope, schedule, and design assumptions

Architecture & Detailed Design Specification

Define architecture and detailed design specifications based on requirements and evaluated trade-offs:

• Author micro-architecture documents: block diagrams, state machine descriptions, data path sketches, interface signal definitions, and timing budgets
• Evaluate architectural trade-offs: soft IP vs. hard IP, VHDL vs. Verilog coding approach, pipeline depth vs. resource utilization, and clock domain strategies
• Define resource estimates (LUT, FF, BRAM, DSP, SERDES) and present architecture proposals at design review gates
• Document all design decisions and rationale in the engineering design record for traceability through to production

2. RTL Micro-Architecture & Coding

Micro-Architecture & Module Coding

Implement synthesizable RTL for assigned modules across a range of design complexity levels:

• Code production-quality RTL in VHDL and/or Verilog: state machines, data path pipelines, control logic, FIFOs, arbiters, and bus interfaces
• Implement high-speed serial protocol logic covering PCIe Gen5/Gen6, USB 3.2, Ethernet 10G/25G/100G, Aurora, and AMBA-AXI interconnects
• Design digital signal processing blocks: FIR/IIR filters, FFT/IFFT pipelines, decimation/interpolation chains, and fixed-point arithmetic units
• Implement memory interface controllers: DDRx, SRAM, and cache management logic optimized for FPGA memory architecture
• Code peripheral and control interfaces: UART, I2C, SPI, USB, and interrupt controllers with software-accessible register maps

Coding Standards & Design Quality

Maintain RTL coding quality and consistency across all assigned design blocks:

• Apply FPGA-appropriate coding styles: synchronous resets, registered outputs, one-hot FSM encoding, and inference of FPGA primitives (BRAM, DSP, SRL)
• Follow design-for-verification and design-for-implementation guidelines: avoid combinational loops, latches, and uncontrolled clock gating
• Perform self-review and participate in peer design reviews before committing RTL to the design baseline

Multiple Clock Domain Design

Design and implement reliable multi-clock domain architectures:

• Design clock domain crossing (CDC) structures: synchronizers, async FIFOs, handshake protocols, and multi-bit CDC strategies
• Define and document all clock relationships; classify paths as synchronous, asynchronous, or false for constraint authoring
• Use CDC analysis tools (Mentor CDC, Cadence Conformal CDC) to verify crossing structures before synthesis

3. Verification & Functional Sign-Off

Testbench Development

Write testbenches for assigned modules achieving complete scenario and corner-case coverage:

• Develop self-checking testbenches in VHDL / SystemVerilog: stimulus generators, response monitors, scoreboards, and coverage collectors
• Write directed tests for nominal operation and constrained-random tests targeting corner cases, protocol violations, and error injection scenarios
• Achieve functional coverage targets: line coverage, branch coverage, FSM state/transition coverage, and toggle coverage prior to sign-off

Simulation & Regression

Execute and manage simulation flows using industry-standard tools:

• Run RTL and gate-level simulations in ModelSim / QuestaSim / Xcelium; analyze waveforms and debug failures to root cause
• Integrate module-level testbenches into team regression suites; triage and resolve failing tests within committed timelines
• Generate and review coverage reports; identify un-exercised scenarios and add targeted tests to close coverage gaps

Protocol & Interface Verification

Verify protocol-level behavior for high-speed interfaces:

• Verify PCIe, USB, Ethernet, AXI, and JESD204B/C interface logic for protocol compliance using BFMs (Bus Functional Models) and VIP
• Validate ADC/DAC interfaces: data capture timing, sample synchronization, and digital front-end alignment
• Document verification results: test coverage matrix, defect log, waiver rationale, and sign-off status per module release

4. FPGA Implementation, Timing Closure & Debugging

FPGA Implementation Flow

Execute the full FPGA implementation flow from RTL through production bitstream:

• Run synthesis in Xilinx Vivado / PlanAhead and Altera Quartus Prime; analyze utilization, timing, and power reports after each run
• Apply physical constraints: pin assignments, I/O standards, Pblock floorplan constraints, and LOC/BEL directives for performance-critical paths
• Execute place & route iterations targeting timing closure at required frequency and resource utilization within platform budget
• Generate and validate production bitstreams; manage bitstream configuration and partial reconfiguration flows where required

Timing Closure

Own timing closure for assigned partitions based on optimization trade-offs:

• Author SDC/XDC timing constraints: create_clock, set_input_delay, set_output_delay, set_multicycle_path, and set_false_path directives
• Analyze timing reports: identify critical paths, understand slack distribution, and apply RTL or constraint changes to resolve violations
• Apply implementation optimizations: pipeline register insertion, logic replication, carry chain usage, and DSP/BRAM packing for density and speed trade-offs
• Iterate through synthesis strategy sweeps and P&R seed exploration to achieve consistent timing closure across design variants

FPGA Debugging & HW/SW Integration

Debug FPGA designs and support hardware and software integration on target platforms:

• Debug FPGA designs on hardware using Chipscope Pro / Vivado Hardware Manager (Xilinx) and Signal Tap Logic Analyzer (Altera/Intel)
• Use external debug equipment: oscilloscopes, logic analyzers, protocol analyzers, and BERTs to isolate signal integrity and functional failures
• Support HW/SW integration: validate register map access, interrupt routing, DMA data transfers, and driver handshake sequences with embedded software
• Diagnose and resolve hardware failures: capture and analyze waveforms, trace data paths, and identify root cause with systematic debug methodology

Required Qualifications

Education & Experience

• Education: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related discipline
• Experience: Hands-on FPGA engineering experience including successful completion of at least one FPGA-based product or platform project
• Project Track Record: Must have contributed to a complete FPGA project lifecycle — from RTL coding through implementation and hardware bring-up. Simulation-only or purely academic experience does not qualify.

Technical Expertise — Core Requirements

RTL Design — Must Have

• Coding experience in VHDL and/or Verilog is mandatory — ability to write clean, synthesizable RTL for data path, control, and interface blocks
• Thorough understanding of FPGA-appropriate coding styles: synchronous design, FSM encoding, BRAM/DSP/SRL inference, and registered output disciplines
• Demonstrated understanding of speed vs. density trade-offs and how RTL coding choices directly affect synthesis and P&R quality of results (QoR)
• Experience designing with multiple clock domains: CDC structures, async FIFOs, synchronizers, and clock domain classification for constraints

FPGA Devices & Tools — Must Have

• Experience targeting Xilinx and/or Altera FPGAs is required — familiarity with UltraScale+, Zynq, Versal (Xilinx/AMD) or Agilex, Stratix 10 (Intel/Altera)
• Proficiency with EDA tools: Xilinx Vivado / PlanAhead and/or Altera Quartus Prime for synthesis, P&R, timing analysis, and bitstream generation
• Simulation tool experience: ModelSim, QuestaSim, or equivalent — ability to run regressions, analyze waveforms, and debug simulation failures
• Hardware debug tool proficiency: Chipscope Pro, Vivado Hardware Manager (Xilinx) and/or Signal Tap Logic Analyzer (Altera); familiarity with logic analyzers, oscilloscopes, and protocol analyzers

High-Speed Serial Interfaces — Core

• Practical RTL implementation experience with high-speed serial protocols: PCIe Gen4/5, USB 3.2, Ethernet 10G/25G/100G, or equivalent
• Experience with AMBA-AXI / AXI4-Stream interconnect fabric for on-chip bus integration and DMA data flow
• Familiarity with transceiver / GT architecture: link training, channel bonding, and protocol initialization sequences

Memory & Peripheral Interfaces — Core

• Experience with memory interfaces: DDRx controller integration, timing constraints, and burst access optimization
• Implementation experience with peripheral interfaces: UART, I2C, SPI, or equivalent register-based control interfaces
• Familiarity with ADC/DAC interfaces for data acquisition and signal processing applications

DSP on FPGA — Appreciated

• Experience in RTL implementation of DSP algorithms: FIR/IIR filters, FFT, decimation/interpolation, and fixed-point arithmetic pipelines
• Understanding of DSP slice usage (DSP48E2 / DSP58) for multiply-accumulate, SIMD, and complex multiply operations
• Exposure to radar, communications, or signal processing applications on FPGA is a strong advantage

Advanced Interfaces — Appreciated

• Development experience with PCIe Gen5/Gen6, CXL, 200G/400G Ethernet, or JESD204B/C for high-bandwidth platform designs
• Experience with AMBA APB, AHB, or CHI interconnect protocols for SoC-style FPGA platform architectures
• Familiarity with Vitis AI / Versal DPU for AI/ML inference deployment on FPGA platforms

Engineering Competencies

Technical Ownership

• Proven ability to own assigned RTL modules from specification through verification sign-off and implementation closure with minimal supervision
• Systematic debug mindset: isolates root cause efficiently in both simulation and hardware using structured analysis techniques
• Maintains design documentation, adheres to coding guidelines, and meets design review and coverage gate targets

Execution Excellence

• Delivers RTL blocks, testbenches, and implementation results on committed schedule, flags risks early with proposed mitigations
• Provides accurate effort estimates for RTL tasks, verification scenarios, and timing closure iterations
• Experienced working within structured development milestones: architecture review, RTL freeze, verification sign-off, and implementation release

Collaboration & Communication

• Communicates design decisions, trade-offs, and implementation risks clearly in design reviews and team discussions
• Writes clear technical documentation: module specifications, timing constraint rationale, testbench coverage reports, and hardware debug notes
• Works effectively with hardware, firmware, and software teams during platform integration, bring-up, and validation phases

Why This Role

• Real Design Complexity: Work on multi-million gate FPGA designs with the latest generation protocols — PCIe Gen5/Gen6, 100G+ Ethernet, JESD204B — not reference designs or eval board exercises
• Product Impact: Your RTL ships in defense systems, 5G test platforms, AI accelerators, and robotics platforms used by Tier-1 customers globally
• Full Lifecycle Ownership: Own modules end-to-end — specification, RTL coding, verification, timing closure, and hardware debug. Real accountability at every stage
• Innovation Mandate: Work at the cutting edge of FPGA-AI convergence with Versal AI Core, UltraScale+, and Agilex platforms integrating AI Engines and custom accelerators
• Career Growth: Clear progression from FPGA Engineer to Senior FPGA Engineer and Principal Engineer with structured mentorship from engineers who have shipped multiple complex products
• Equity Upside: Meaningful ESOP allocation in a company transitioning from bootstrapped to VC-backed growth

Compensation & Benefits

• Salary commensurate with relevant experience, expertise, and skills.
• Performance Bonus: Annual bonus tied to individual delivery milestones and team OKRs
• Benefits: Health insurance, flexible work options, and paid leaves.
• Equity: ESOP allocation commensurate with seniority and contribution