Mobiveil ASIC Design Engineer interview questions

Once written test qualified , they called for interview In the interview process, they were asking me to solve 10 verilog programming questions, 10 puzzles In technical interview questions are design of Mux, clock generations, 2s complement design , swapping of two numbers using blocking and non blocking , parity checker design. one questions is , given the RTL code for that design the net-list circuit