Hardware Design Engineer applicants have rated the interview process at STMicroelectronics with 4 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 100% positive. To compare, the company-average is 76.7% positive. This is according to Glassdoor user ratings.
Candidates applying for Hardware Design Engineer roles take an average of 31 days to get hired, when considering 2 user submitted interviews for this role. To compare, the hiring process at STMicroelectronics overall takes an average of 14 days.
Common stages of the interview process at STMicroelectronics as a Hardware Design Engineer according to 2 Glassdoor interviews include:
One on one interview: 50%
Skills test: 50%
Here are the most commonly searched roles for interview reports -
Primo colloquio per meta' conoscitivo e meta' tecnico. Alcuni domande vertevano su come individuare un difetto in un semplice circuito combinatorio o la struttura di sincronizzatori di clock. Secondo colloquio puramente tecnico in merito all'elettronica digitale e low power come la dipendenza dei consumi di un micro dalla frequenza, tensione, switching activity. Terzo colloquio HR finale.
I applied through university. The process took 4 weeks. I interviewed at STMicroelectronics (Arzano, Campania) in Mar 2022
Interview
Colloquio tecnico basato su domande di architettura dei sistemi integrati (esame universitario). Si entra nel tecnico e vedono molto la volontà di ragionamento. Le persone che lavorano lì dentro sono molto competenti e buone dal punto di vista umano
I applied through university. The process took 1 day. I interviewed at STMicroelectronics (New Delhi) in Mar 2017
Interview
I applied on campus. There were three rounds. One written other technical and last HR. Written was objective questions based on digital analog and cmos. Technical round was more digital and cmos based. Some practical questions on sequential circuits were asked. Overall it was good. Interviewers were warm and friendly.
Interview questions [1]
Question 1
setup hold time violations, flipflop ckt, sequential circuits,