STMicroelectronics IP Verification Engineer interview questions
Updated 15 Oct 2015
based on 1 rating
Difficulty
Average
Experience
Very positive
How others got an interview
100%
Applied online
Applied online
Interview search
1 interviews
STMicroelectronics interviews FAQs
IP Verification Engineer applicants have rated the interview process at STMicroelectronics with 3 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 100% positive. To compare, the company-average is 76.7% positive. This is according to Glassdoor user ratings.
Common stages of the interview process at STMicroelectronics as a IP Verification Engineer according to 1 Glassdoor interviews include:
Group panel interview: 100%
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I applied online. I interviewed at STMicroelectronics
Interview
I got call from HR and asked to schedule interview on next day. Interview questions are on Topics - Digital design, Verilog, specific protocol knowledge, Systemverilog, OOPS, UVM and apptitude. It was not a tough interview. They also asked about the project I prepared during my internship and Set up and Hold concept related questions.
Interview questions [1]
Question 1
Basic questions related to Digital design, Verilog, specific protocol, Systemverilog, OOPS, UVM and apptitude.