Recent salaries shared by ASIC Design Verification Engineer at PerfectVIPs
Job title | Years of Experience
Total Pay
Base • Additional pay
Location
Date submitted
Job title | Years of Experience
Location
Date submitted
Total Pay
Base • Additional pay
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PerfectVIPs pay FAQs
- The average salary for an ASIC Design Verification Engineer is ₹8,00,000 per year (estimate) in India, which is 33% lower than the average PerfectVIPs salary of ₹12,00,000 per year (estimate) for this job.
- PerfectVIPs employees working as an ASIC Design Verification Engineer in India have attributed a compensation and benefits rating of 2.7 out of 5 stars, based on 18 ratings. This is 4% lower than the average of ASIC Design Verification Engineer professionals at PerfectVIPs worldwide.
- The salary trajectory of a an ASIC Design Verification Engineer ranges between locations and employers. The salary starts at ₹6,99,430 per year (estimate) and goes up to ₹36,75,000 per year (estimate) for the highest level of seniority.
- The estimated average salary for a ASIC Design Verification Engineer at PerfectVIPs is ₹9,50,000 per year or ₹457 per hour, but some professionals have reported earning up to roughly ₹31,04,000 per year (90th percentile). The typical pay range is between ₹5,11,250 (25th percentile) and ₹18,25,000 (75th percentile) annually. This is based on 26 salaries submitted by PerfectVIPs ASIC Design Verification Engineer professionals on Glassdoor, as of Jun 2026.