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      Cadence Design Systems

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      Design Engineer Interview

      6 Jun 2021
      Anonymous employee
      Accepted offer
      Positive experience
      Difficult interview

      Application

      I applied online. I interviewed at Cadence Design Systems

      Interview

      Role: Hardware Level C coding for DSP Requirements: Experience in DSP, Neural Networks, C and Assembly Language Experience: The Interviewers were very friendly and helped me to answer some questions. C coding is the most important part of this job. Then comes knowledge on DSP and so on.

      Interview questions [1]

      Question 1

      Interview Round 1: Questions 1. Tell me about yourself. 2. I did an image enhancement project and hence the interviewer asked me which filter to use to detect edges. ANS- High pass filter 3. Difference between IIR and FIR filter. Which is stable? Can we make an FIR filter unstable by any means? 4. What is a histogram? Write a C code to find the histogram from an image. (I made an array of 256 elements and store values in it). Interviewer asked that if the image had only pixel values from 0 till 100, memory is wasted. What alternative do you suggest? Can you use malloc? Also, if you assign a variable for every pixel value, how do identify which variable corresponds to which variable (ANS- it is not possible) 5. Difference between heap and stack 6. What is static variable? What is volatile in C? 7. You are given an array of 20 elements {a1,a2,a3..a20}. Write a C program to modify the array in such a manner that the elements of new array looks like {a1,a11,a2,a12,…a10,a20} without using another array. 8. Puzzle questions- (i) There are 25 horses. How many races are to be performed to determine top 5 position. (ans-7) (ii) There are 10 bags will lots of balls. Out of that one bag has balls with 9 grams. All others weigh 10 grams. There is one weighing machine available. How many weighing should you perform to identify the odd bag. (ans-1) Interview Round 2: Questions 1. Tell me about yourself. 2. What is memory hole in C? (memory leakage is different) (ans) ( Try creating a struct with int and char. The size is supposed to be 4+1=5. But sizeof() will show 8. This is due to memory hole) 3. What is static variable and static function? 4. Difference between malloc and calloc. 5. Write a C program to identify number of set bits in a number? What happens if the input is a signed number? 6. There is an array of 10 elements, each having 32 bits. The data is stored in Little endian format in C. Write a C function which will accept the number of bits to be returned from the beginning of array. Eg. If the input is 7 bits, it should return 7 bits from the first element and the current position is saved. Now if input is 10, it should take 10 bits from current bits and return. So current position will be 17. Now if the input is 32, it should take 16 bits from first element and 15 from second element and combine it meaningfully and return. 7. What is sampling? Explain Nyquist criteria for sampling 8. Difference between FIR and IIR filters. Interview Round 3 Questions 1. Tell me about yourself. 2. Interviewer asked me about my projects. I explained my final year project (it was based on image processing). Interviewer asked me should the results and explain it. 3. Asked about other projects in my resume. 4. Write a C program to flip an image along its right edge. HR round Questions 1. Tell me about yourself. 2. How were the interviews. What is the one thing which you learned from these interviews. 3. What is the one thing which you were not able to answer in the interview? Did you study it later? 4. What is your biggest achievement? Tell any one idea which you had, which was difficult to implement, but you successfully implemented it. 5. Tell me about any innovation which you did 6. Why do you want this job? Why do you want to leave previous company? Prepare well and don’t be tensed. All the best!!
      Answer question
      9

      Other Design Engineer interview reviews for Cadence Design Systems

      Design Engineer Interview

      12 Sept 2025
      Anonymous interview candidate
      Hyderābād
      No offer
      Positive experience
      Difficult interview

      Application

      I interviewed at Cadence Design Systems (Hyderābād)

      Interview

      Interview is bit different from other companies. Overall experience is good. Gave my best. Prepare well on the basis of verilog sv and sta.overall experience is good. And prepare your previous projects as well.

      Interview questions [1]

      Question 1

      About static timing analysis in detail
      Answer question

      Design Engineer Interview

      2 Apr 2025
      Anonymous interview candidate
      Belo Horizonte, Minas Gerais
      No offer
      Neutral experience
      Average interview

      Application

      I applied online. The process took 3 weeks. I interviewed at Cadence Design Systems (Belo Horizonte, Minas Gerais) in Mar 2025

      Interview

      Entrevista RH. Entrevista técnica em inglês com breve apresentação do CV em seguida coding interview em SystemVerilog, Python e C. Basicamente programar e explicar o que estava fazendo e o por quê.

      Interview questions [1]

      Question 1

      Qual a diferença entre = e <= em SV?
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      Design Engineer Interview

      18 Oct 2024
      Anonymous interview candidate
      Bengaluru
      No offer
      Neutral experience
      Difficult interview

      Application

      I applied online. I interviewed at Cadence Design Systems (Bengaluru)

      Interview

      Held in VCET Puttur. 700+ registrations, out of that around 45 got shortlisted for 2nd round Day1 : Two Pen & Paper rounds Complex network theory circuits Day 2: 3 rounds of technical interview

      Interview questions [1]

      Question 1

      Most of the questions were related to network theory .
      Answer question
      2