1st technical round: Cmos "and" gate draw and explain If i interchange all nmos with pmos and vice versa in the following and gate. What functionality will i obtain(ignore the logic reduction) Verilog code for dflipflop Sensitivity list Asynchronous vs synchronous reset Why is setup time usually larger than hold time? Setup and hold time violations. Which is more dangerous (harder to fix) What is metastability? Explain D Flipflop using transmission gate and using d latch Go-to vs call instruction Explain Interrupt Service routine Microprocessor vs microcontrollers based on performance metrics 2nd technical round: project discussion 4:1MUX using 2:1MUX Xor using 2:1MUX Applications of xor functionality in communication systems Any microcontroller you know that uses MUX and explain how it uses and for what it uses Demux application Explain ring counter and johnson counter Priority encoder explain Verilog code for t flipflop with reset Setup time hold time explain. And what steps would you take to overcome violations What affects frequency of clock? setup time or hold time? Bulb with 2 switches. toggling one switch will change state of bulb irrespective of present state of the other switch. Which logic gate would u visualize this