Very disappointing process. Initially position was advertised in Germany but then changed to Budapest. It felt like there was already pre-selected candidate for the position. I was given to write UVM verification plan for AHB-slave to SRAM. Assignment was sent to me 5:50pm Friday so there was no-one to clarify. I completed it anyway making RTL code with transaction level model for verification (not UVM though). But on the actual interview I asked about home assignment but was told it was sent to me by mistake. The interview questions were random. I observed complete lack of enthusiasm from the interviewers. We haven't discussed things like transaction level models, flow control and microarchitecture, although I tried to spark this conversation. I was refused without adequate feedback provided.

Il y a un test tres technique d'une heure puis on voit une dizaine de personne, chacun pendant 1/2 heure. Les questions lors des entretiens sont tres techniques et il y a des exercices a faire sur tableau: exercice de design, de software en langage C, un entretien en anglais pour voir le niveau. Ces tests de connaissances sont assez decorreles du travail de tous les jours, et ne permettent pas forcement de deceler le potentiel ni la motivation de quelqu'un.