Had 2 round, 1st telephonic and 2nd on-site interview with 5 team members. I was contacted by the hiring manager for a phone interview and sent me job description. After scheduling, got a call and the interview lasted for about 45-50 min. Interviewer asked various design questions, timing questions, setup time, hold time, synthesis flow, input/output delay etc. After all the questions I asked interviewer about the position in detail and interviewer told the position would focus on front-end ASIC designing, synthesis, timing analysis as indicated by the job description. After a week, I was contacted for further interview(onsite) by HR and again provided me with the job description details (Design). I went to the office and started with the interview. The first interviewer asked me some verification questions and oops concept. I was surprised. Later, I was told that I am being interviewed for a design verification position. All the further rounds had verification questions and some design questions. They asked OOPS concepts, system verilog, assertions, arrays, test plans, AMBA Buses etc.