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ASIC Engineer Interview Questions

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Differentiate between = and => sings in verilog.

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As far as I remember,first is simultaneous assignment and the other is sequential. In reality, every flip flop is made of = inside, => sign is just to simulate sequential code to carry out verification.

= is blocking statemnt whereas <= is non blocking statemnt.. so basically dealing = solves serially nd <= solves paralley.

using a simple logic gate, convert a SET type flop to a RESET type flop

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Why were you looking for switch so early from your current organization?

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How to process a high rate signal in low frequency clock.

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Salary negotiation. Do not hesitate to ask more than industry standard, no matter what is your current CTC

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Psychological and Analytic questions would take a conscious presence of mind to go through, The question includes technical knowledge with twists

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Sequence Detector , 3 bit mangnitude comparator , C pattern problem, counter based problem

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Draw a T flip flop using simple gates.

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Asked to design a FSM

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Mainly focused on Low power as I said I am interested in low power. Asked about timing analysis STA setup hold and synthesis. Some basic rtl design with verilog vhdl.Basic CMOS modeling NAND gate and NOR gate. IN HR round as i was fail in one of the subject was asking about that subject but as i performed well they consider that.

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