ASIC engineer interview questions shared by candidates
Differentiate between = and => sings in verilog.
As far as I remember,first is simultaneous assignment and the other is sequential. In reality, every flip flop is made of = inside, => sign is just to simulate sequential code to carry out verification.
= is blocking statemnt whereas <= is non blocking statemnt.. so basically dealing = solves serially nd <= solves paralley.
Mainly focused on Low power as I said I am interested in low power. Asked about timing analysis STA setup hold and synthesis. Some basic rtl design with verilog vhdl.Basic CMOS modeling NAND gate and NOR gate. IN HR round as i was fail in one of the subject was asking about that subject but as i performed well they consider that.