ASIC Engineer Interview Questions |

ASIC Engineer Interview Questions


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Differentiate between = and => sings in verilog.

2 Answers

As far as I remember,first is simultaneous assignment and the other is sequential. In reality, every flip flop is made of = inside, => sign is just to simulate sequential code to carry out verification.

= is blocking statemnt whereas <= is non blocking statemnt.. so basically dealing = solves serially nd <= solves paralley.

using a simple logic gate, convert a SET type flop to a RESET type flop

3 Answers

Why were you looking for switch so early from your current organization?

1 Answer

How to process a high rate signal in low frequency clock.

1 Answer

Salary negotiation. Do not hesitate to ask more than industry standard, no matter what is your current CTC

1 Answer

Psychological and Analytic questions would take a conscious presence of mind to go through, The question includes technical knowledge with twists

1 Answer

Sequence Detector , 3 bit mangnitude comparator , C pattern problem, counter based problem

1 Answer

Draw a T flip flop using simple gates.

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Asked to design a FSM

1 Answer

Mainly focused on Low power as I said I am interested in low power. Asked about timing analysis STA setup hold and synthesis. Some basic rtl design with verilog vhdl.Basic CMOS modeling NAND gate and NOR gate. IN HR round as i was fail in one of the subject was asking about that subject but as i performed well they consider that.

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