Rfic design engineer Interview Questions

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Rfic Design Engineer interview questions shared by candidates

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Qualcomm
RFIC Design Engineer was asked...10 January 2017

Perform a simple impedance match between two impedances.

2 Answers

Could you please help us by sharing more interview questions of that particular interview. It will help us to prepare. Less

How long did they take to extend you an offer from the date of interview?

pSemi

Why do we use cascoding amplifier?

1 Answers

High output resistance. High isolation from output (prevent instability). Reduced miller capacitance. Less

pSemi

What determines switching speed?

1 Answers

Ron Coff time constant

pSemi

FET Vds max is 3V but your bias is 10V, what do you do to use this bias voltage?

1 Answers

Stack multiple transistors

SpaceX

Describe the biasing scheme you used for an LNA project, and why you chose that biasing scheme.

1 Answers

I used a bandgap reference because it created a stable biasing point to help matching. Less

pSemi

Why can you get lower loss with silicon on insulator?

1 Answers

Less parasitic body capacitances

Skyworks Solutions

Smith charts for LNA matching + LNA design (gain/NF/IIP3 optimization) + Inductor design + RF Switch design + OpAmps/LDOs + Bandgaps

1 Answers

all text book questions. Make sure to review LNA design and basic analog concepts Less

Microchip Technology

Since I work for a big RFIC giant in San Diego and Microchip had to compete with it therefore their questions seemed not focused on testing me rather were focused on my experience. They tried hard to learn and get a word out of me regarding my current experience but I kept it professional . After they failed they declined me an offer saying that they could not get high compensation aligning with my experience.

1 Answers

I would recommend don't waste you time finding a job especially in San Diego RFIC analog group at Microchip, as I found them pretty novice and you can never gain a proudful experience working their. It's mainly a hiding spot for people not willing to grow and work with low compensation for a long time. Less

Qualcomm

Some questions about the architecture of receiver system, like why nowadays passive mixer is preferred than active one.

Qualcomm

Phone interview was about 15 to 20 questions in 45 minutes. I would most definitely recommend studying Razavi's 2nd edition analog design textbook whether you are applying for RFIC or Mixed Signal. Half of questions I was asked are on fundamental things starting from MOS transistors and device physics to Op amp design and Bandgap. The other half were on my specialties. If you are a PLL designer, you will be asked synthesizer questions. If you are an ADC designer, you will be asked ADC... and so on. Some of the questions that kept showing up through these interviews from both Qualcomm and other companies were the impedance transformation by MOSFET: what happens to the impedance of a resistor when it is in series with a MOSFET gate, drain, or source (source degeneration, input impedance of CG amplifier, CD amplifier, and so on). Bandgap will probably be asked. Impedance matching, if RFIC. I think that the outcome of the interview is highly dependent on the quality of the research presentation. If one claims to have done a design of such and such blocks, then one is expected to know pretty much everything about the block.

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