• Design digital signal processing pipelines for signal detection, classification, and extraction
• Develop algorithms for delay estimation, frequency shift analysis, and phase-based measurements
• Implement multi-channel correlation and synchronization pipelines
• Design and implement DDC/DUC architectures for wideband signal capture
• Develop RTL pipelines (VHDL/Verilog) for high-throughput real-time processing
• Interface with high-speed ADC/DAC systems (JESD, LVDS, etc.)
• Optimize latency, throughput, and power for onboard processing
• Enable real-time data reduction and preprocessing before downlink
• Support SDR-based prototyping and simulation environments

• Strong DSP and statistical signal processing foundation
• FPGA design (VHDL/Verilog/SystemVerilog)
• Python, MATLAB, C/C++ for modeling and validation
• Understanding of real-time systems and high-speed data pipelines

Requirements

• 4-6 years in signal processing, FPGA, or RF sensing systems
• Experience in SDR, spectrum monitoring, or remote sensing domains
• Exposure to working with non-ideal or low SNR signal environments