Cpu Design Engineer Interviews

Cpu Design Engineer Interview Questions

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Qualcomm
CPU Design Verification Engineer was asked...6 May 2012

Pipelining Hazards?

1 Answers

Hazards are problems with the instruction pipeline in CPU micro-architectures, when the next instruction cannot execute in the following clock cycle and can potentially lead to incorrect computation results. There are typically three types of hazards data hazards structural hazards control hazards (branching hazards) There are several methods used to deal with hazards, including pipeline stalls/pipeline bubbling, operand forwarding, and in the case of out-of-order execution, the scoreboarding method and the Tomasulo algorithm. Source:Wiki Less

Intel Corporation

Draw a state diagram for a given pattern. If even number if 0's come as input, then the output is asserted on every even consecutive 1. If odd number if 0's come as input, then the output is asserted on every odd consecutive 1.

1 Answers

I had drawn the state diagram which he said was correct but also told me that it could have been done with lesser number of states. Less

Qualcomm

Do you know anything about RISC Architecture?

1 Answers

RISC(Reduced Instruction Set Computing) - is a CPU design strategy based on the insight that "simplified instruction set" provides higher performance with a microprocessor architecture(micro-architecture) capable of executing them using fewer cycles per instruction(CPI). This is opposed to Complex Instruction Set (CISC) computing. A general RISC system uses small, highly optimized set of instructions rather than a more versatile set of instructions.Another common trait is that RISC systems use the load/store architecture, where memory is normally accessed only through specific instructions, rather than accessed as part of other instructions like add. Well-known RISC families include MIPS(ISA),RISC(Berkeley's RISC implementation) in SPARC, Power (including PowerPC), DEC Alpha, AMD 29k, ARM, Intel i860 and i960. (Edited) Source - Wiki Less

Intel Corporation

Describe a situation when you would use a Direct mapped cache over a set associative cache.

1 Answers

Is it for instruction caches ?

Intel Corporation

compare tradeoffs of 10 wide vs. 4x 2.5 wide parallel transistors. Made me think.

1 Answers

Better matching with another transistor if properly layout is done..

Futurewei Technologies

Have you had experience in CPU physical layout design?

Apple

Self introduction + Project introduction + Questions about projects' details + Cache coherency protocols including MESI + Cache placement algorithm + Virtual Memory + Code analysis + Programming + Group Introduction + Questions

Intel Corporation

Draw the layout (stick diagram) for an AND_OR circuit?

Intel Corporation

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