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Digital design engineer Interview Questions

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What is setup hold time

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Setup time is the time the data should be held constant before the arrival of the clock edge.

Set Up time is Minimum Amount of time During which Data Signal Should be Stable Before the Clock made a Valid[Low-to-High] Transition. Hold time is the Minimum Amount of time After the Clock Made a Valid Transition During which Data Signal Should Stable.

FSM FLIP FLOP, VLSI BASICS , SET UP HOLD TIME AND ASK IN DETAIL ABOUT DIGITAL CIRCUITS AND ALL ABOUT DIGITAL INTREGRATED CIRCUITS.Qualcomm paper consisted of three sections. The first section had general aptitude questions. I cannot suggest anything on this. The second section was on programming which had basic questions on C ranging from datatypes to pointers. The first year course on computer applications is enough to answer most of the questions. You can expect questions on sorting techniques, structures, pointers, and finding asymptotic complexity and output of the given code. We had questions on the source of compile time or run time errors in a program and correcting the code for proper execution. The third section had basic electronics questions, both analog and digital. It was much simpler than that of TI. The main concepts to be good at are gates minimization, multiplexers, decoders, Canonical expressions, flip-flops, counters, BJTs. Both TI and Qualcomm may have a question or two on general topics such as maximum power transfer theorem, variation of parameters with temperature given the temperature co-efficient, which can be directly solved by data given. So, working on basics will definitely help you a lot to clear the tests. 14k Views · 142 Upvotes Upvote142

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Asynchronous FIFO depth calculation, System verilog testbench overview

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Q1: Aptitude (trick) questions related to trains

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Design a divide by 3 counter.

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FIFO depth given a design of 50W/100 cycles and 5R/10 cycles.

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They asked mostly implementation of Fourier transforms and digital circuits

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They asked about microprocessor and about some combinational and sequential circuits related questions

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Questions on Logic Design, Comp. architecture, static timing analysis, Latches, flip flops, CMOS, Mosfets, RC circuits, and few questions from C and Algorithms.

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Digital logic gates, cirucit design, inverters

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