RTL design (Verilog/System Verilog),MATLAB/Simulink modeling.

Your Role

Key responsibilities in your new role

• Spec extraction, designing and implementation of DSP algorithms in MATLAB/Simulink.
• Definition of architecture and translation of MATLAB/Simulink models into synthesizable Verilog/System Verilog RTL.
• Optimization of the algorithms and the converted RTL for performance, power & area efficiency.
• Technical expertise in Digital Design, Architecture & Front-End flow.
• Engagement with various cross functional teams including Verification, Analog, Back-End, Marketing, Validation to ensure alignment on design objectives.
• Coaching and Mentorship of junior colleagues to foster quality and technical expertise.

Your Profile

Qualifications and skills to help you succeed

• Bachelor's or Master's degree in a relevant field, such as Electronics, Digital Design, VLSI, SoC Design, Signal Processing.
• Good Understanding of Back-End flows including PNR, STA.
• Strong Communication skills to interact with Cross functional teams and lead execution teams.
• Good understanding of serial protocols like I2C, SPI, UART, PMBUS
• Exposure to Point of Load converters, Gate driver controllers, PMICs etc.
• Preferable understanding of Automotive Functional Safety standards.
• 12+ years of experience in RTL design (Verilog/System Verilog),MATLAB/Simulink modeling.
• Strong fundamentals in digital signal processing with exposure to fixed-point & Floating-point math.
• Strong technical knowledge of Front-End flows including Linting, CDC,RDC, Timing Constraints, Power intent, Synthesis, DFT, ATPG, Fault Grading, LEC, MVRC.

Contact:
Jyoti.Vimal@Infineon.com

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