THE ROLE:

As a SoC Program Manager, you will lead end-to-end execution across complex System-on-Chip (SoC/ASIC) development programs from architecture through tapeout and post-silicon phases. You will drive program milestones, manage cross-functional dependencies across IP teams (CPU/GPU/NOC/DDR/SoC subsystems), and ensure alignment across RTL, PD, DFT, firmware, validation, and platform teams. You will be responsible for planning, tracking, reporting, and risk management across all phases of SoC execution, including architecture, design convergence, validation, tapeout, and silicon enablement, while ensuring predictable delivery and high-quality outcomes.

THE PERSON:

You bring strong execution discipline, structured program management, and cross-functional leadership. You partner seamlessly with architects, IP owners, RTL, PD, DFT, firmware, validation, and external vendors to drive convergence, resolve dependencies, and maintain schedule integrity. You understand system-level architecture, SoC integration challenges, milestones (e.g., architecture, RTL feature completion, physical design readiness, validation readiness, engineering change order (ECO) phase, tapeout) and the full lifecycle of complex SoC programs, with the ability to drive alignment across geographically distributed teams. You ensure execution is on-time, within cost, and manage scope changes. As a Program Manager you will drive AMD product solution deliverables and alignment with customers’ platforms to ensure highest level customer satisfaction throughout their product lifecycle. You proactively involve team members in planning, decision-making and execution efforts.

KEY RESPONSIBILITIES:

• Program Planning & Execution

• Define, structure, and drive end-to-end SoC program plans in alignment with architecture, design, and tapeout milestones.

• Ensure requirements are clearly defined and integrated into design, validation, and silicon execution plans.

• Create and maintain detailed schedules covering:

• Architecture definition and high-level design readiness

• IP integration and subsystem convergence

• Design milestones (architecture, RTL feature completion, physical design readiness, validation readiness, engineering change order (ECO) phase, tapeout)

• Track progress across IP teams (CPU, NOC, DDR, SoC subsystems, etc.) and ensure timely milestone completion.

• Drive disciplined execution through structured action tracking, meeting cadences, and program reviews.

• Drive milestone checklist compliance and readiness reviews for key program exits.

• Manage resource planning, onboarding, and execution tracking across internal teams and external vendors (ODC/CW engagement).

• Cross-Functional Collaboration

• Work closely with architecture, RTL, PD, DFT, firmware, validation, and system engineering teams to resolve cross-domain dependencies.

• Drive convergence forums (IP-SOC, subsystem syncs, CFT reviews) to ensure alignment across all stakeholders.

• Track and manage detailed schedules and deliverable lists covering:

• Cross-IP dependency tracking (interfaces, fuse mapping, metal stack, etc.)

• Validation readiness (pre-silicon and post-silicon)

• Silicon bring-up and platform readiness

• Risk & Issue Management

• Identify program risks early (schedule slips, dependency gaps, design readiness, vendor execution issues).

• Drive mitigation plans with clear ownership; escalate proactively to leadership when required.

• Track cross-IP blockers and ensure timely resolution through structured follow-up and governance.

• Manage backlog of open items, track closure rates, and ensure high-priority issues are driven to closure.

• Reporting & Governance

• Collect, analyze, and publish program status and execution metrics (milestone health, dependency closure, risk status).

• Maintain dashboards and trackers using Jira, Confluence, Excel, PowerBI, and internal tools.

• Provide concise, executive-level weekly / monthly updates highlighting risks, progress, and key asks.

• Run structured governance cadences including CFT forums, leadership reviews, and cross-team syncs.

• Process & Methodology Improvement

• Drive improvements in program execution frameworks, action tracking, and cross-team coordination.

• Introduce structured templates for meeting notes, tracking, and reporting to improve clarity and efficiency.

• Streamline workflows to reduce noise, eliminate duplication, and improve execution predictability.

• Implement automation for reporting, tracking, and data consolidation using tools like MS Project, Jira, and scripting.

• Leverage AI for improving execution efficiency across tracking, reporting, and workflows

• AI focused execution mindset

• Focus on using AI to automate existing processes and improve execution efficiency

• Hands-on experience with AI tools

• Experience using AI with Excel, PowerPoint, and Jira is a plus

PREFERRED EXPERIENCE:

• Must have experience in SoC/ASIC product cycles and understanding of architecture, integration, validation, and silicon bring-up phases.

• Strong familiarity with SoC / IP execution flows:

• Architecture to tapeout lifecycle (standard RTL and netlist-based milestones)

• IP integration and dependency management

• Pre-silicon and post-silicon execution flows

• System-level bring-up and platform readiness

• Detail-oriented, self-driven with a strong sense of pride and ownership.

• Proficiency in project management tools (JIRA, Confluence, PowerBI, Excel, MS Project, AI tools).

• Strong organizational, problem-solving, interpersonal, presentation, written and verbal communication skills.

• Ability to build relationships and work effectively as a self-starter and as part of a team.

• Prior experience driving large multi-site or multi-vendor engagements is desirable.

• People management experience is desirable.

• Excellent verbal and written communication skills to handle all levels of interaction, including executive level.

• Horizontal leadership/Matrix management experience.

• Technical program management and customer relationship management.

ACADEMIC CREDENTIALS:

Bachelor’s or Master’s degree in Computer/Electrical/Electronics Engineering

Formal project management education, PMP / Scrum Master